View CY62146EV30LL-45BVXI_2830962.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy62146ev30 mobl ? 4-mbit (256k x 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05567 rev. *c revised march 26, 2007 features ? very high speed: 45 ns ? wide voltage range: 2.20v?3.60v ? pin compatible with cy62146dv30 ? ultra low standby power ? typical standby current: 1 a ? maximum standby current: 7 a ? ultra low active power ? typical active current: 2 ma @ f = 1 mhz ? easy memory expansion with ce , and oe features ? automatic power down when deselected ? cmos for optimum speed and power ? available in a pb-free 48-ball vfbga and 44-pin tsop ii packages functional description [1] the cy62146ev30 is a high performance cmos static ram organized as 256k words by 16 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power do wn feature that significantly reduces power consumption by 80% when addresses are not toggling. the device can also be put into standby mode reducing power consumption by more than 99% when deselected (ce high). the input and output pins (io 0 through io 15 ) are placed in a high impedance state when: ? deselected (ce high) ? outputs are disabled (oe high) ? both byte high enable and byte low enable are disabled (bhe , ble high) ? write operation is active (ce low and we low) write to the device by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from io pins (io 0 through io 7 ), is written into the location specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from io pins (io 8 through io 15 ) is written into the location specified on the address pins (a 0 through a 17 ). read from the device by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on io 0 to io 7 . if byte high enable (bhe ) is low, then data from memory appears on io 8 to io 15 . see the ?truth table? on page 9 for a complete description of read and write modes. product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1 mhz f = f max min typ [2] max typ [2] max typ [2] max typ [2] max cy62146ev30ll 2.2 3.0 3.6 45 ns 2 2.5 15 20 1 7 notes: 1. for best practice recommendations, please refer to the cypress application note system design guidelines on http://www.cypress.com . 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25c. [+] feedback [+] feedback
cy62146ev30 mobl ? document #: 38-05567 rev. *c page 2 of 12 logic block diagram pin configurations [3, 4] 256k x 16 ram array io 0 ?io 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 io 8 ?io 15 ce we bhe a 16 a 0 a 1 a 9 a 10 ble a 17 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 15 a 16 a 8 a 9 a 10 a 11 a 13 a 14 a 12 oe bhe ble ce we io 0 io 1 io 2 io 3 io 4 io 5 io 6 io 7 io 8 io 9 io 10 io 11 io 12 io 13 io 14 io 15 v cc v cc v ss v ss nc 10 a 17 48-ball vfbga 44-pin tsop ii top view top view we a 11 a 10 a 6 a 0 a 3 ce io 10 io 8 io 9 a 4 a 5 io 11 io 13 io 12 io 14 io 15 v ss a 9 a 8 oe a 7 io 0 bhe nc a 2 a 1 ble io 2 io 1 io 3 io 4 io 5 io 6 io 7 a 15 a 14 a 13 a 12 nc nc nc 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss a 17 notes: 3. nc pins are not connected on the die. 4. pins h1, g2, and h6 in the bga package are address ex pansion pins for 8 mb, 16 mb and 32 mb, respectively. [+] feedback [+] feedback
cy62146ev30 mobl ? document #: 38-05567 rev. *c page 3 of 12 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .............. .............. .... ?65c to + 150c ambient temperature with power applied ........ ............... .............. ...... ?55c to + 125c supply voltage to ground potential .............................?0.3v to + 3.9v (v ccmax + 0.3v) dc voltage applied to outputs in high-z state [5, 6] ................?0.3v to 3.9v (v ccmax + 0.3v) dc input voltage [5, 6] ........... ?0.3v to 3.9v (v cc max + 0.3v) output current into outputs (low) ............................ 20 ma static discharge voltage ......................................... >2001v (per mil-std-883, method 3015) latch-up current ....... .............. .............. .............. .... >200 ma operating range device range ambient temperature v cc [7] cy62146ev30 industrial ?40c to +85c 2.2v to 3.6v electrical characteristics (over the operating range) parameter description test conditions 45 ns unit min typ [2] max v oh output high voltage i oh = ?0.1 ma 2.0 v i oh = ?1.0 ma, v cc > 2.70v 2.4 v v ol output low voltage i ol = 0.1 ma 0.4 v i ol = 2.1 ma, v cc > 2.70v 0.4 v v ih input high voltage v cc = 2.2v to 2.7v 1.8 v cc + 0.3 v v cc = 2.7v to 3.6v 2.2 v cc + 0.3 v v il input low voltage v cc = 2.2v to 2.7v ?0.3 0.6 v v cc = 2.7v to 3.6v ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max), i out = 0 ma cmos levels 15 20 ma f = 1 mhz 2 2.5 i sb1 automatic ce power down current ? cmos inputs ce > v cc ? 0.2v, v in > v cc ?0.2v or v in < 0.2v f = f max (address and data only), f = 0 (oe , bhe , ble and we ), v cc = 3.60v 17 a i sb2 [8] automatic ce power down current ? cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.60v 17 a notes: 5. v il(min) = ?2.0v for pulse durations less than 20 ns. 6. v ih(max) = v cc + 0.75v for pulse durations less than 20 ns. 7. full device ac operation assumes a minimum of 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. 8. only chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating. [+] feedback [+] feedback
cy62146ev30 mobl ? document #: 38-05567 rev. *c page 4 of 12 capacitance (for all packages) [9] parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance [9] parameter description test conditions vfbga package tsop ii package unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 75 77 c/w jc thermal resistance (junction to case) 10 13 c/w ac test loads and waveforms parameters 2.50v 3.0v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics (over the operating range) parameter description conditions min typ [2] max unit v dr v cc for data retention 1.5 v i ccdr [8] data retention current v cc = 1.5v, ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v 0.8 7 a t cdr [9] chip deselect to data retention time 0 ns t r [10] operation recovery time t rc ns data retention waveform v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v all input pulses r th r1 equivalent to: thevenin equivalent v cc(min) v cc(min) t cdr v dr > 1.5v data retention mode t r v cc ce notes: 9. tested initially and after any design or process changes that may affect these parameters. 10. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. [+] feedback [+] feedback
cy62146ev30 mobl ? document #: 38-05567 rev. *c page 5 of 12 switching characteristics (over the operating range) [11, 12] parameter description 45 ns unit min max read cycle t rc read cycle time 45 ns t aa address to data valid 45 ns t oha data hold from address change 10 ns t ace ce low to data valid 45 ns t doe oe low to data valid 22 ns t lzoe oe low to low-z [13] 5ns t hzoe oe high to high-z [13, 14] 18 ns t lzce ce low to low-z [13] 10 ns t hzce ce high to high-z [13, 14] 18 ns t pu ce low to power up 0ns t pd ce high to power down 45 ns t dbe ble / bhe low to data valid 22 ns t lzbe ble / bhe low to low-z [13] 5ns t hzbe ble / bhe high to high-z [13, 14] 18 ns write cycle [15] t wc write cycle time 45 ns t sce ce low to write end 35 ns t aw address setup to write end 35 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 35 ns t bw ble / bhe low to write end 35 ns t sd data setup to write end 25 ns t hd data hold from write end 0 ns t hzwe we low to high-z [13, 14] 18 ns t lzwe we high to low-z [13] 10 ns n otes: 11. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3 ns (1v/ns) or less, ti ming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? on page 4 . 12. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. plea se see application note an13842 for further clarification. 13. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 14. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedence state. 15. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data in put setup and hold timing must be referenced to the edge of t he signal that terminates the write. [+] feedback [+] feedback
cy62146ev30 mobl ? document #: 38-05567 rev. *c page 6 of 12 switching waveforms read cycle 1 (address transition controlled) [16, 17] read cycle no. 2 (oe controlled) [17, 18] previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t lzbe t lzce t pu high impedance i cc t hzoe t hzce t pd t hzbe t lzoe t dbe t doe impedance high i sb data out oe ce v cc supply current bhe /ble address notes: 16. the device is continuously selected. oe , ce = v il , bhe and/or ble = v il . 17. we is high for read cycle. 18. address valid before or similar to ce and bhe , ble transition low. [+] feedback [+] feedback
cy62146ev30 mobl ? document #: 38-05567 rev. *c page 7 of 12 write cycle no. 1 (we controlled) [15, 19, 20] write cycle no. 2 (ce controlled) [15, 19, 20] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc t hzoe data in note 21 t bw t sce data io address ce we oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe data in t bw t sa ce address we data io oe bhe /ble note 21 notes: 19. data io is high impedance if oe = v ih . 20. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 21. during this period, the ios are in output state and input signals must not be applied. [+] feedback [+] feedback
cy62146ev30 mobl ? document #: 38-05567 rev. *c page 8 of 12 write cycle no. 3 (we controlled, oe low) [20] write cycle no. 4 (bhe /ble controlled, oe low) [20] switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 21 ce address we data io bhe /ble t hd t sd t sa t ha t aw t wc data in t bw t sce t pwe t hzwe t lzwe note 21 data io address ce we bhe /ble [+] feedback [+] feedback
cy62146ev30 mobl ? document #: 38-05567 rev. *c page 9 of 12 truth table ce we oe bhe ble inputs/outputs mode power h x x x x high-z deselect/power down standby (i sb ) l x x h h high-z output disabled active (i cc ) l h l l l data out (io 0 ?io 15 ) read active (i cc ) l h l h l data out (io 0 ?io 7 ); io 8 ?io 15 in high-z read active (i cc ) l h l l h data out (io 8 ?io 15 ); io 0 ?io 7 in high-z read active (i cc ) l h h l l high-z output disabled active (i cc ) l h h h l high-z output disabled active (i cc ) l h h l h high-z output disabled active (i cc ) l l x l l data in (io 0 ?io 15 ) write active (i cc ) l l x h l data in (io 0 ?io 7 ); io 8 ?io 15 in high-z write active (i cc ) l l x l h data in (io 8 ?io 15 ); io 0 ?io 7 in high-z write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 45 CY62146EV30LL-45BVXI 51-85150 48-ball vfbga (pb-free) industrial cy62146ev30ll-45zsxi 51-85087 44-pin tsop ii (pb-free) please contact your local cypress sales repr esentative for availability of other parts [+] feedback [+] feedback
cy62146ev30 mobl ? document #: 38-05567 rev. *c page 10 of 12 package diagrams figure 1. 48-ball vfbga (6 x 8 x 1 mm), 51-85150 a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 51-85150-*d [+] feedback [+] feedback
cy62146ev30 mobl ? document #: 38-05567 rev. *c page 11 of 12 ? cypress semiconductor corporation, 2006-2007. the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under pate nt or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express writt en agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support system s where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufa cturer assumes all risk of such use and in doing so indemni fies cypress against all charges. figure 2. 44-pin tsop ii, 51-85087 mobl is a registered trademark, and more battery life is a tr ademark of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 51-85087-*a [+] feedback [+] feedback
cy62146ev30 mobl ? document #: 38-05567 rev. *c page 12 of 12 document history page document title:cy62146ev30 mobl ? , 4-mbit (256k x 16) static ram document number: 38-05567 rev. ecn no. issue date orig. of change description of change ** 223225 see ecn aju new data sheet *a 247373 see ecn syt changed advance information to preliminary moved product portfolio to page 2 changed v cc stabilization time in footnote #8 from 100 s to 200 s removed footnote #14(t lzbe ) from previous revision changed i ccdr from 2.0 a to 2.5 a changed typo in data retention characteristics(t r ) from 100 s to t rc ns changed t oha from 6 ns to 10 ns for both 35 ns and 45 ns speed bin changed t hzoe , t hzbe , t hzwe from 12 to 15 ns for 35 ns speed bin and 15 to 18 ns for 45 ns speed bin changed t sce and t bw from 25 to 30 ns for 35 ns speed bin and 40 to 35 ns for 45 ns speed bin changed t hzce from 12 to 18 ns for 35 ns speed bin and 15 to 22 ns for 45 ns speed bin changed t sd from 15 to 18 ns for 35 ns speed bin and 20 to 22 ns for 45 ns speed bin changed t doe from 15 to 18 ns for 35 ns speed bin changed t dbe from 15 to 18 ns for 35 ns speed bin changed ordering information to include pb-free packages *b 414807 see ecn zsd changed from preliminary information to final changed the address of cypress semiconductor corporation on page #1 from ?3901 north first street? to ?198 champion court? removed 35ns speed bin removed ?l? version of cy62146ev30 changed ball e3 from dnu to nc removed the redundant foot note on dnu. changed i cc (max) value from 2 ma to 2.5 ma and i cc (typ) value from 1.5 ma to 2 ma at f=1 mhz changed i cc (typ) value from 12 ma to 15 ma at f = f max changed i sb1 and i sb2 typ values from 0.7 a to 1 a and max values from 2.5 a to 7 a. changed the ac test load capacitance from 50pf to 30pf on page# 4 changed i ccdr from 2.5 a to 7 a. added i ccdr typical value. changed t lzoe from 3 ns to 5 ns changed t lzce and t lzwe from 6 ns to 10 ns changed t lzbe from 6 ns to 5 ns changed t hzce from 22 ns to 18 ns changed t pwe from 30 ns to 35 ns. changed t sd from 22 ns to 25 ns. updated the package diagram 48-ball vfbga from *b to *d updated the ordering information table and replaced the package name column with package diagram. *c 925501 see ecn vkn added footnote #8 related to i sb2 and i ccdr added footnote #12 related ac timing parameters [+] feedback [+] feedback

▲Up To Search▲

Price & Availability of CY62146EV30LL-45BVXI

	To Download CY62146EV30LL-45BVXI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .